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Showing posts with label Driver Circuit. Show all posts
Showing posts with label Driver Circuit. Show all posts

Friday, May 14, 2010

Fully Differential, Mono, Ceramic Speaker Driver Circuit


This is a design circuit for speaker driver circuit. This circuit is based on LM48556 as controller the circuit. This is the figure of the circuit;



The LM48556 is a single supply, mono, ceramic speaker driver with an integrated charge-pump, designed for portable devices, such as cell phones, where board space is at a premium. The LM48556 charge pump allows the device to deliver 17.5VPP (typ) from a single 4.5V supply. Additionally, the charge pump features a soft start function that minimizes transient current during power-up.

The LM48556 features high power supply rejection ratio (PSRR) of 80dB at 217Hz, allowing the device to operate in noisy environments without additional power supply conditioning. Flexible power supply requirements allow operation from 2.7V to 5.0V. Additionally, the LM48556 features a differential input function and an externally configurable gain. A low power shutdown mode reduces supply current consumption to 0.1μA.

Superior click and pop suppression eliminates audible transients on power-up/down and during shutdown. The LM48556 is available in an ultra-small 12-bump micro SMD package (2mm x 1.5mm).

[Schematic circuit source: National Semiconductor Notes]

Monday, March 29, 2010

Line Driver Power Supply Circuit

This is a design circuit for power supply that based on LM1578 single chip IC. The LM1578A Switching Regulator can be used to convert the already existing supply into a separate ±12V supply for powering the interface line drivers. This is the figure of the circuit.


The power supply, shown in the figure operates from an input voltage as low as 4.2V, and delivers an output of ±12V at ±40 mA with an efficiency of better than 70%. The circuit provides a load regulation of ±1.25% (from 10% to 100% of full load) and a line regulation of ±0.08%. Other notable features include a cycle-by-cycle current limit and an output voltage ripple of less than 40 mVp-p. A unique feature of this flyback regulator is its use of feedback from BOTH outputs. This dual feedback configuration results in a sharing of the output voltage regulation by each output so that one output is not left unregulated as in single feedback systems. In addition, since both sides are regulated, it is not necessary to use a linear regulator for output regulation.

[Schematic circuit source: National Semiconductor Notes]

Wednesday, March 24, 2010

AC Mode Universal Motor Drive

This is a design circuit for AC mode universal motor drive circuit that is suitable for large range of application. It uses the microcontroller to interpret the user interface that is used to select the four operating modes that are defined in hardware. This is the figure of the circuit.


As power switch, this circuit use “SNUBBERLESS” TRIAC BTA 12-600BW with a maximum specified gate trigger current of 50mA at 25°C. It is driven by pulse. A small signal transistor interfaces the “SNUBBERLESS” TRIAC and the microcontroller. If spurious triggering is prohibited in case of mains perturbation we should implement a small filter RfCf, although no snubber is needed in nominal operations. For synchronization, this circuit uses zero voltage detection across the mains. We can change operation from 50Hz to 60Hz by changing the EPROM/ROM table defining TRIAC conduction angle versus power level. It can be self-adapted by software or hardware programmed.

[Circuit schematic source: STMicroelectronics Application Note].

Sunday, January 24, 2010

Cascaded Timer Using 4528 IC

This is a design circuit that uses a CMOS dual re-trigger mono stable IC 4528 in a cascade timer i. The CMOS timer can be easily cascaded with other similar 4528 circuits to lengthen the timing needed. This is the figure of the circuit.


The timing of the project is determine by VR3 and C1 for the first stage and VR4 and C2 for the second stage. Once button S1 is pressed, the 1st stage output pin 6 logic level will go high and output pin 7 will go low for the preset time which is determined by VR3 and C1. When the time is up, the output pin 6 will go low and pin 7 high. At this moment of time, pin 7 will positive trigger the 2nd stage of the timer at pin 12. Output pin 10 will go high and pin 9 will go low for a time determine by VR4 and C2 before the cycle end with pin 10 back to low and pin 9 to high.

Tuesday, October 20, 2009

Driving Capacitive Loads Circuit

This is a simple circuit design for capacitive load driver. This circuit is built by LF155. LF155 is an op amps that is feature low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. This is the figure of the circuit.


For make this circuit, we need resistor 5K if we used this op amps. This is due to a unique output stage design, these amplifiers have the ability to drive large capacitive loads and still maintain stability. CL(MAX) 0.01μF. This circuit has overshoot ≤ 20%

Driving Capacitive Load Circuit

This is a one design circuit for low impedance loads circuit using driving the capacitive loads. This circuit is combine the high output current required to slew large capacitances with appropriate frequency compensation. This circuit is based on LT1210 for control and amplified the signal input. This is the figure of the circuit.


Bridging can be used to increase the output power transferred to a transformer. Differential operation also promotes the cancellation of even-order distortion. In the figure is shown a differential application using an LT1207 as a bridge driver for HDSL. [Schematic source: Linear Technology Corporation, Inc].

Input Buffer and Output Driver for Surround Sound

This circuit is design to reduce the signal level applied to the delay chip, to prevent any risk of overload. Since the maximum specified level is 1 Volt RMS, it is important to ensure that the signal is below this at all times. The output from a CD player is generally about 2.5V (maximum), so the input circuit reduces the level by a factor of about 3.5 (10.8dB). This is a simple design for input and output driver. This is the figure of the circuit.


Since this must be amplified again after the delay, there is a pre-emphasis circuit included to increase the level of high frequencies. The frequency response is restored to normal with treble cut after the delay, reducing noise as well. This technique is used with FM radio broadcasts, vinyl disks and in many other areas and is effective in minimizing noise levels. The resistor marked "SoT" (Select on Test) is designed to allow for the fact that the gain or loss through the delay circuit is not necessarily unity, but can vary. This is designed only to compensate for units with a lower than normal gain, and might be as low as 15k for the worst case. This is unlikely, so if desired, the resistor may be omitted altogether, or a 100k pot can be used to allow the gain to be changed easily.

Sunday, October 11, 2009

Low Noise Audio Line Driver Circuit

This is design for audio line driver circuit. This circuit is based on LT1206 IC. LT1206 has been naturally selected as the components for video application since it has suitable bandwidth and output derive capability. This high performance features is not only suitable for video application, but also make it definitely suitable for audio application. This is the figure of the circuit.


The circuit diagram shows that the LT1206 combined with the LT1115 low distortion, very low noise audio buffer with a gain of 10. With a 5VRMS and 32 Ohm load (780mW), the THD + noise for the circuit is only 0.0009% at 1kHz, rising to 0.004% at 20kHz. The frequency response is flat to 0.1dB from DC to 600kHz, with a – 3dB bandwidth of 4MHz. The circuit is stable with capacitive loads of 250pF or less.

[Schematic diagram source: Linear Technology Application Notes]

Laser Diode Driver Circuit

This is circuit design for a laser diode driver can be implemented using voltage-controlled current source. This simple linear laser diode driver gives cleaner drive current than a switched (PWM) drivers. This circuit is based on OPA350 IC. This is the figure of the circuit.


A Howland current pump with a current booster is used as the basic of this laser diode driver. Q1 is used as the current booster on the output of a R-R CMOS OPA350 op amp (U2). Voltage drop across a shunt resistor (RSHUNT) in series with the laser diode is measured differentially to sense the current. An analog voltage from a potentiometer of from a microprocessor controlled DAC can be fed to VIN to control the laser diode current. Using the component values as shown, the scale factor is 1V input equals 1A output.

[Schematic diagram source: Burr-Brown Products Application Report]
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