This is a design circuit that uses a CMOS dual re-trigger mono stable IC 4528 in a cascade timer i. The CMOS timer can be easily cascaded with other similar 4528 circuits to lengthen the timing needed. This is the figure of the circuit.
The timing of the project is determine by VR3 and C1 for the first stage and VR4 and C2 for the second stage. Once button S1 is pressed, the 1st stage output pin 6 logic level will go high and output pin 7 will go low for the preset time which is determined by VR3 and C1. When the time is up, the output pin 6 will go low and pin 7 high. At this moment of time, pin 7 will positive trigger the 2nd stage of the timer at pin 12. Output pin 10 will go high and pin 9 will go low for a time determine by VR4 and C2 before the cycle end with pin 10 back to low and pin 9 to high.
The timing of the project is determine by VR3 and C1 for the first stage and VR4 and C2 for the second stage. Once button S1 is pressed, the 1st stage output pin 6 logic level will go high and output pin 7 will go low for the preset time which is determined by VR3 and C1. When the time is up, the output pin 6 will go low and pin 7 high. At this moment of time, pin 7 will positive trigger the 2nd stage of the timer at pin 12. Output pin 10 will go high and pin 9 will go low for a time determine by VR4 and C2 before the cycle end with pin 10 back to low and pin 9 to high.
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